1. Field of the Invention
The present invention relates to a wafer processing method which can provide a sufficient die strength and gettering effect on each device constituting a wafer.
2. Description of the Related Art
A plurality of devices such as ICs and LSIs are formed on the front side of a wafer so as to be partitioned by a plurality of crossing division lines. The back side of the wafer is ground to reduce the thickness of the wafer to a predetermined thickness. Thereafter, the wafer is divided into the individual devices by using a dicing apparatus and the devices thus obtained are used for various electronic equipment or the like. Further, a package device also called an MCP (Multi-Chip Package) generally improved in function is also put to practical use (see Japanese Patent Laid-open No. 2009-26992, for example). This package device is fabricated by grinding the back sides of plural wafers to reduce the thickness of each wafer to 100 μm or less and next stacking these wafers so as to connect terminals (electrodes) formed on the upper and lower devices of the stacked wafers.
Regardless of whether or not the wafers are stacked, each device is formed on the front side of a silicon substrate and the back side of the silicon substrate is ground to reduce the thickness of the wafer to a predetermined thickness. Thereafter, the silicon substrate is cut by dicing to obtain the individual devices. However, when the back side of the wafer is ground, a grinding strain is left on the back side of the wafer to cause a reduction in die strength of each device. To cope with this problem, there has been proposed a technique such that the back side of the wafer subjected to back grinding is polished by using a polishing pad to remove the grinding strain, thereby improving the die strength of each device (see Japanese Patent Laid-open No. 2006-80329, for example).